搜索资源列表
da_fir
- 基于verilog的分布式算法FIR滤波器 有两个文件 一个用来生成查找表-FIR filter using Distributed Algorithm.
my_fir
- Verilog 写的FIR滤波器，modelsim仿真通过-Verilog write FIR filter, modelsim simulation through
FIR_Lowpass
- 用Verilog HDL编写的FIR低通滤波器。FIR低通滤波器采用8阶串行方式实现。-Written using Verilog HDL FIR low-pass filter. FIR low-pass filter 8-order serial.
filter
- verilog implementation of structural FIR filter. Contains testbench, including sample data and coefficients.
da_fir
- 基于FPGA分布式算法FIR滤波器verilog代码 （本人 小论文 代码，通过验证） 本文提出一种新的FIR滤波器FPGA实现方法。讨论了分布式算法原理，并提出了基于分布式算法FIR滤波器的实现方法。通过改进型分布式算法结构减少硬件资源消耗，用流水线技术提高运算速度，采用分割查找表方法减小存储规模，并在Matlab和Modelsim仿真平台得到验证。 为了节省FPGA逻辑资源、提高系统速度，设计中引入了分布式算法实现有限脉冲响应滤波器(F
filter
- verilog—FIR滤波器程序，可移植性强，可以借助FDAtool设计滤波器系数，写到本程序里即可-verilog-FIR filter process, portability, and can make use of FDAtool design filter coefficients, the program can be written to
filter_signed_and_unsigned
- FIR滤波器的verilog语言实现（输入为8bit有符号以及无符号两种，滤波器为8阶，截止频率约在6*pi/7）-FIR filter verilog language (input 8bit signed and unsigned are two 8-order filter cut-off frequency is about 6* pi/7)
proiect
- Fir filter implemented in verilog and tasted. also conteins the implementation in simulink
fir_filter_50Mhz
- 基于并行分布式算法的高速Fir滤波器的设计代码，采用Verilog编写，压缩包为quartus II编译过的工程代码-Parallel and distributed algorithms based on a high-speed Fir filter design code, Verilog prepared, compressed package for the quartus II compiled project code
fir_lowpass
- 简易FIR低通滤波器的verilog代码-Simple FIR low-pass filter verilog code
FIR_FILTER
- FIR滤波器的verilog实现，包含testbench，以及设计文档，文档里面详细介绍了滤波器系数的求取-FIR filter verilog implementation, including testbench, and the design document, the document which details the filter coefficients to strike
FIR_dida
- 自己写的FIR滤波器设计，verilog语言写的，很好用-Write your own FIR filter design, verilog language, easy to use
FIRverilog
- 多种FIR滤波器的verilog语言实现 (数字信号处理的FPGA实现)-Verilog language variety FIR filter implementation (digital signal processing FPGA implementation)
16QAM
- 使用verilog编写的16QAM调制解调代码，可用于quartus和ISE，因为不包含FIR，只能用于仿真，不能用于实际通信-Verilog prepared using 16QAM modulation and demodulation code can be used quartus and ISE, because they do not contain FIR, only for simulation and not for actual communication
fir4btp
- 4tap FIR filter in verilog code
FILTER
- VERILOG CODE FOR 1D FIR FILTER IMPLIMENTATION -VERILOG CODE FOR 1D FIR FILTER IMPLIMENTATION
2D-FILTER
- VERILOG CODE FOR 2D FIR FILTER
fir_verilog_matlab
- 本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。-This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design re
code
- 用Verilog写的采用LSM算法的自适应性FIR滤波器，有testbench和主体代码，亲测可用-Written using Verilog LSM algorithm using adaptive FIR filters, and the body has testbench code, pro-test available
fir16.v
- 16阶FIR滤波器设计的verilog代码-Verilog 16-order FIR filter